The decrease in cell capacitance which typically occurs when the area of a memory cell is decreased poses a serious obstacle to the continued increase in integration levels of DRAMs. The decrease in cell capacitance impedes the operation of devices at low voltages, lowers the reading ability of a memory cell and increases soft error rate.
The amount of charge Q which can be stored in a capacitor is equal to a product of the capacitor capacitance C and the voltage V applied across the capacitor. That is, Q=C.times.V. Thus, to obtain a predetermined amount of charge at decreased operation voltages, the capacitance should be increased. Assuming that the effective area of a capacitor is A, a dielectric constant in vacuum is .epsilon..sub.0, the relative dielectric constant of the dielectric .epsilon..sub.r, and the thickness of the dielectric is d, the capacitance C is equal to A.epsilon..sub.0 .epsilon..sub.r /d. Therefore, the capacitor capacitance C increases with increases in effective area A, a larger relative dielectric constant .epsilon..sub.r, and a smaller thickness d of the dielectric layer.
To increase the effective area of a capacitor, three-dimensional lower electrode structures have been suggested. However, it is typically difficult to apply these three-dimensional lower electrode structures in real situations since their manufacturing processes are complicated and defects are likely to occur during the manufacturing processes.
Accordingly, research has been actively conducted on making a thin film of a material of a high dielectric constant to be used as a capacitor dielectric. A capacitor having a thin film of high dielectric constant is more preferred in terms of high integration level as well as process simplification because a capacitor comprises a high dielectric constant material can have a sufficient capacitance with a simple two-dimensional lower electrode structure.
However, when a lower electrode is formed of impurity-doped polysilicon as in the prior art, materials having high dielectric constants may react with polysilicon and cause the formation of a dielectric layer having a very low dielectric constant at the interface with the lower electrode. Therefore, there is an increasing need for new structures of a lower electrode which are suitable for capacitors to which a thin film of a high dielectric constant is applied.
FIGS. 1, 2, and 3 are sectional views for explaining a conventional method for manufacturing a capacitor of a semiconductor device. FIG. 1 illustrates the step of forming an interlayer insulating layer pattern 20 and a contact plug 30. The interlayer insulating layer pattern 20 is formed on a semiconductor substrate 10 to have a contact hole exposing a predetermined area of the semiconductor substrate 10. Subsequently, an impurity-doped polysilicon layer is formed on the resultant structure having the interlayer insulating layer pattern 20, to fill the contact hole. Then, the contact plug 30 is formed in the contact hole by completing etching the polysilicon layer till the interlayer insulating layer pattern 20 is exposed.
FIG. 2 illustrates the step of completing a lower electrode comprising the contact plug 30, a diffusion barrier layer pattern 40, and a conductive layer pattern 50 by forming the diffusion barrier layer 40 and the conductive layer pattern 50. First, a diffusion barrier layer and a conductive layer are sequentially formed of a titanium nitride (TiN) and platinum (Pt), respectively, on the resultant structure having the contact plug 30 formed therein.
Then, the diffusion barrier layer pattern 40 and the conductive layer pattern 50 are formed to be sequentially stacked on the contact plug 30 by sequentially etching the conductive layer and the diffusion barrier layer till the interlayer insulating layer pattern 20 is exposed. Thus, the lower electrode comprises the contact plug 30, the diffusion barrier layer pattern 40, and the conductive layer pattern 50. The diffusion barrier layer pattern 40 serves to prevent the capacitance of the capacitor to be formed from decreasing in response to a reaction between the contact plug 30 and the conductive layer pattern 50 in a subsequent dielectric forming process.
FIG. 3 illustrates the step of completing the capacitor by forming a dielectric layer 60 and an upper electrode 70. First, an amorphous dielectric layer containing Ba, Sr, Ti, and O is formed on the structure having the lower electrode formed thereon by chemical vapor deposition (CVD) or sputtering. Then, the structure including the amorphous dielectric layer is heat-treated at 500-750.degree. C. so that the amorphous dielectric layer is crystallized. Thus, a crystalline dielectric layer 60 is formed of (Ba, Sr)TiO.sub.2 of a perovskite structure. The crystalline dielectric layer 60 is referred to as the dielectric layer 60, hereinafter.
Alternatively, the dielectric layer 60 can be formed in an in-situ method where materials respectively containing Ba, Sr, Ti, and O are deposited on the structure including the lower electrode, while the structure including the lower electrode is being heat-treated at 500-750.degree. C. Then, the upper electrode 70 is formed on the dielectric layer 60, thus completing the capacitor. Thus, the dielectric forming step is typically accompanied by the above-described heat treatment. Since a sidewall A of the diffusion barrier layer pattern 40 makes contact with the amorphous dielectric layer containing oxygen, oxygen penetrates into the sidewall A of the diffusion barrier layer pattern 40 during the heat treatment step and causes oxidation of the diffusion barrier layer pattern 40 and the contact plug 30 which results in the formation of materials having a low dielectric constants such as TiO.sub.2 and SiO.sub.2. In addition, when the dielectric layer 60 is formed in-situ, the diffusion barrier layer pattern 40 and the contact plug 30 are also oxidized because the sidewall of the diffusion barrier layer pattern 40 is exposed to an oxygen atmosphere. The diffusion barrier layer pattern 40 and the contact plug 30 may also be oxidized by oxygen penetrating through the conductive layer pattern 50 and into the diffusion barrier layer pattern 40.
Consequently, according to conventional methods for manufacturing a capacitor for a semiconductor device, though the diffusion barrier layer pattern 40 prevents the contact plug 30 and the conductive layer pattern 50 from reacting at their interface, oxygen penetrating into the sidewall of the diffusion barrier layer pattern 40 and the conductive layer pattern 50 during the step of forming the dielectric layer 60 may oxidize the diffusion barrier layer pattern 40 and the contact plug 30, thus producing materials of low dielectric constants such as TiO.sub.2 and SiO.sub.2. As a result, the capacitance of the capacitor may be reduced.